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-rw-r--r--package/gcc/10.2.0/0001-arc-Refurbish-adc-sbc-patterns.patch242
-rw-r--r--package/gcc/10.2.0/0002-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch325
-rw-r--r--package/gcc/7.5.0/0001-uclibc-conf.patch29
-rw-r--r--package/gcc/7.5.0/0002-arm-softfloat-libgcc.patch45
-rw-r--r--package/gcc/7.5.0/0003-cilk-fix-build-without-wchar.patch64
-rw-r--r--package/gcc/7.5.0/0004-Revert-2016-01-21-Ajit-Agarwal-ajitkum-xilinx.com.patch42
-rw-r--r--package/gcc/7.5.0/0005-PR-target-81497-Fix-arm_acle.h-for-C.patch323
-rw-r--r--package/gcc/7.5.0/0006-gcc-define-_REENTRANT-for-RISC-V-when-pthread-is-pas.patch31
-rw-r--r--package/gcc/7.5.0/0007-xtensa-fix-PR-target-91880.patch49
-rw-r--r--package/gcc/8.4.0/0002-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch322
-rw-r--r--package/gcc/9.3.0/0005-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch325
-rw-r--r--package/gcc/Config.in.host15
-rw-r--r--package/gcc/arc-2020.09-release/0001-arc-Refurbish-adc-sbc-patterns.patch243
-rw-r--r--package/gcc/arc-2020.09-release/0100-uclibc-conf.patch (renamed from package/gcc/arc-2020.03-release/0100-uclibc-conf.patch)0
-rw-r--r--package/gcc/gcc.hash4
-rw-r--r--package/gcc/gcc.mk44
16 files changed, 1488 insertions, 615 deletions
diff --git a/package/gcc/10.2.0/0001-arc-Refurbish-adc-sbc-patterns.patch b/package/gcc/10.2.0/0001-arc-Refurbish-adc-sbc-patterns.patch
new file mode 100644
index 0000000000..ed7b000ede
--- /dev/null
+++ b/package/gcc/10.2.0/0001-arc-Refurbish-adc-sbc-patterns.patch
@@ -0,0 +1,242 @@
+From 09944fba5bfb8e5543ce043c70d08222cf2f97ff Mon Sep 17 00:00:00 2001
+From: Claudiu Zissulescu <claziss@synopsys.com>
+Date: Wed, 11 Nov 2020 12:31:10 +0200
+Subject: [PATCH] arc: Refurbish adc/sbc patterns
+
+The adc/sbc patterns were unecessary spliting, remove that and
+associated functions.
+
+gcc/ChangeLog:
+
+2020-10-11 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc-protos.h (arc_scheduling_not_expected): Remove
+ it.
+ (arc_sets_cc_p): Likewise.
+ (arc_need_delay): Likewise.
+ * config/arc/arc.c (arc_sets_cc_p): Likewise.
+ (arc_need_delay): Likewise.
+ (arc_scheduling_not_expected): Likewise.
+ * config/arc/arc.md: Convert adc/sbc patterns to simple
+ instruction definitions.
+
+Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
+Signed-off-by: Veronika Kremneva <kremneva@synopsys.com>
+---
+ gcc/config/arc/arc-protos.h | 3 --
+ gcc/config/arc/arc.c | 53 -------------------------
+ gcc/config/arc/arc.md | 95 ++++++++++++++-------------------------------
+ 3 files changed, 29 insertions(+), 122 deletions(-)
+
+diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
+index c72d78e3b9e..de4cf47c818 100644
+--- a/gcc/config/arc/arc-protos.h
++++ b/gcc/config/arc/arc-protos.h
+@@ -90,10 +90,7 @@ extern void split_subsi (rtx *);
+ extern void arc_split_move (rtx *);
+ extern const char *arc_short_long (rtx_insn *insn, const char *, const char *);
+ extern rtx arc_regno_use_in (unsigned int, rtx);
+-extern bool arc_scheduling_not_expected (void);
+-extern bool arc_sets_cc_p (rtx_insn *insn);
+ extern int arc_label_align (rtx_insn *label);
+-extern bool arc_need_delay (rtx_insn *insn);
+ extern bool arc_text_label (rtx_insn *insn);
+
+ extern bool arc_short_comparison_p (rtx, int);
+diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
+index fcb83c4e23e..2daf83dd009 100644
+--- a/gcc/config/arc/arc.c
++++ b/gcc/config/arc/arc.c
+@@ -10341,59 +10341,6 @@ arc_attr_type (rtx_insn *insn)
+ return get_attr_type (insn);
+ }
+
+-/* Return true if insn sets the condition codes. */
+-
+-bool
+-arc_sets_cc_p (rtx_insn *insn)
+-{
+- if (NONJUMP_INSN_P (insn))
+- if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))
+- insn = seq->insn (seq->len () - 1);
+- return arc_attr_type (insn) == TYPE_COMPARE;
+-}
+-
+-/* Return true if INSN is an instruction with a delay slot we may want
+- to fill. */
+-
+-bool
+-arc_need_delay (rtx_insn *insn)
+-{
+- rtx_insn *next;
+-
+- if (!flag_delayed_branch)
+- return false;
+- /* The return at the end of a function needs a delay slot. */
+- if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
+- && (!(next = next_active_insn (insn))
+- || ((!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) != SEQUENCE)
+- && arc_attr_type (next) == TYPE_RETURN))
+- && (!TARGET_PAD_RETURN
+- || (prev_active_insn (insn)
+- && prev_active_insn (prev_active_insn (insn))
+- && prev_active_insn (prev_active_insn (prev_active_insn (insn))))))
+- return true;
+- if (NONJUMP_INSN_P (insn)
+- ? (GET_CODE (PATTERN (insn)) == USE
+- || GET_CODE (PATTERN (insn)) == CLOBBER
+- || GET_CODE (PATTERN (insn)) == SEQUENCE)
+- : JUMP_P (insn)
+- ? (GET_CODE (PATTERN (insn)) == ADDR_VEC
+- || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
+- : !CALL_P (insn))
+- return false;
+- return num_delay_slots (insn) != 0;
+-}
+-
+-/* Return true if the scheduling pass(es) has/have already run,
+- i.e. where possible, we should try to mitigate high latencies
+- by different instruction selection. */
+-
+-bool
+-arc_scheduling_not_expected (void)
+-{
+- return cfun->machine->arc_reorg_started;
+-}
+-
+ /* Code has a minimum p2 alignment of 1, which we must restore after
+ an ADDR_DIFF_VEC. */
+
+diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
+index d4d9f59a3ea..6c09c86884f 100644
+--- a/gcc/config/arc/arc.md
++++ b/gcc/config/arc/arc.md
+@@ -2857,43 +2857,25 @@ archs4x, archs4xd"
+ (set_attr "type" "compare")
+ (set_attr "length" "4,4,8")])
+
+-; w/c/c comes first (rather than w/0/C_0) to prevent the middle-end
+-; needlessly prioritizing the matching constraint.
+-; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional
+-; execution is used where possible.
+-(define_insn_and_split "adc"
+- [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w")
+- (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0))
+- (match_operand:SI 1 "nonmemory_operand"
+- "%c,0,c,0,cCal"))
+- (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))]
++(define_insn "adc"
++ [(set (match_operand:SI 0 "register_operand" "=r, r,r,r, r,r")
++ (plus:SI
++ (plus:SI
++ (ltu:SI (reg:CC_C CC_REG) (const_int 0))
++ (match_operand:SI 1 "nonmemory_operand" "%r, 0,r,0,Cal,r"))
++ (match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I, r,Cal")))]
+ "register_operand (operands[1], SImode)
+ || register_operand (operands[2], SImode)"
+ "@
+- adc %0,%1,%2
+- add.cs %0,%1,1
+- adc %0,%1,%2
+- adc %0,%1,%2
+- adc %0,%1,%2"
+- ; if we have a bad schedule after sched2, split.
+- "reload_completed
+- && !optimize_size && (!TARGET_ARC600_FAMILY)
+- && arc_scheduling_not_expected ()
+- && arc_sets_cc_p (prev_nonnote_insn (insn))
+- /* If next comes a return or other insn that needs a delay slot,
+- expect the adc to get into the delay slot. */
+- && next_nonnote_insn (insn)
+- && !arc_need_delay (next_nonnote_insn (insn))
+- /* Restore operands before emitting. */
+- && (extract_insn_cached (insn), 1)"
+- [(set (match_dup 0) (match_dup 3))
+- (cond_exec
+- (ltu (reg:CC_C CC_REG) (const_int 0))
+- (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))))]
+- "operands[3] = simplify_gen_binary (PLUS, SImode, operands[1], operands[2]);"
++ adc\\t%0,%1,%2
++ add.cs\\t%0,%1,1
++ adc\\t%0,%1,%2
++ adc\\t%0,%1,%2
++ adc\\t%0,%1,%2
++ adc\\t%0,%1,%2"
+ [(set_attr "cond" "use")
+ (set_attr "type" "cc_arith")
+- (set_attr "length" "4,4,4,4,8")])
++ (set_attr "length" "4,4,4,4,8,8")])
+
+ ; combiner-splitter cmp / scc -> cmp / adc
+ (define_split
+@@ -3025,7 +3007,7 @@ archs4x, archs4xd"
+ DONE;
+ }
+ emit_insn (gen_sub_f (l0, l1, l2));
+- emit_insn (gen_sbc (h0, h1, h2, gen_rtx_REG (CCmode, CC_REG)));
++ emit_insn (gen_sbc (h0, h1, h2));
+ DONE;
+ ")
+
+@@ -3040,44 +3022,25 @@ archs4x, archs4xd"
+ (set_attr "type" "cc_arith")
+ (set_attr "length" "4")])
+
+-; w/c/c comes first (rather than Rcw/0/C_0) to prevent the middle-end
+-; needlessly prioritizing the matching constraint.
+-; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional execution
+-; is used where possible.
+-(define_insn_and_split "sbc"
+- [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w")
+- (minus:SI (minus:SI (match_operand:SI 1 "nonmemory_operand"
+- "c,0,c,0,cCal")
+- (ltu:SI (match_operand:CC_C 3 "cc_use_register")
+- (const_int 0)))
+- (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))]
++(define_insn "sbc"
++ [(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r,r,r,r")
++ (minus:SI
++ (minus:SI
++ (match_operand:SI 1 "nonmemory_operand" "r, 0,r,0, r,Cal")
++ (ltu:SI (reg:CC_C CC_REG) (const_int 0)))
++ (match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I,Cal,r")))]
+ "register_operand (operands[1], SImode)
+ || register_operand (operands[2], SImode)"
+ "@
+- sbc %0,%1,%2
+- sub.cs %0,%1,1
+- sbc %0,%1,%2
+- sbc %0,%1,%2
+- sbc %0,%1,%2"
+- ; if we have a bad schedule after sched2, split.
+- "reload_completed
+- && !optimize_size && (!TARGET_ARC600_FAMILY)
+- && arc_scheduling_not_expected ()
+- && arc_sets_cc_p (prev_nonnote_insn (insn))
+- /* If next comes a return or other insn that needs a delay slot,
+- expect the adc to get into the delay slot. */
+- && next_nonnote_insn (insn)
+- && !arc_need_delay (next_nonnote_insn (insn))
+- /* Restore operands before emitting. */
+- && (extract_insn_cached (insn), 1)"
+- [(set (match_dup 0) (match_dup 4))
+- (cond_exec
+- (ltu (reg:CC_C CC_REG) (const_int 0))
+- (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1))))]
+- "operands[4] = simplify_gen_binary (MINUS, SImode, operands[1], operands[2]);"
++ sbc\\t%0,%1,%2
++ sub.cs\\t%0,%1,1
++ sbc\\t%0,%1,%2
++ sbc\\t%0,%1,%2
++ sbc\\t%0,%1,%2
++ sbc\\t%0,%1,%2"
+ [(set_attr "cond" "use")
+ (set_attr "type" "cc_arith")
+- (set_attr "length" "4,4,4,4,8")])
++ (set_attr "length" "4,4,4,4,8,8")])
+
+ (define_insn "sub_f"
+ [(set (reg:CC CC_REG)
+--
+2.16.2
+
diff --git a/package/gcc/10.2.0/0002-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch b/package/gcc/10.2.0/0002-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch
new file mode 100644
index 0000000000..6f11713c6b
--- /dev/null
+++ b/package/gcc/10.2.0/0002-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch
@@ -0,0 +1,325 @@
+From 472472ee0aaccb6389747d6281c34c558bcca7d8 Mon Sep 17 00:00:00 2001
+From: Romain Naour <romain.naour@gmail.com>
+Date: Wed, 20 Jan 2021 23:26:29 +0100
+Subject: [PATCH] Revert "re PR target/92095 (internal error with -O1
+ -mcpu=niagara2 -fPIE)"
+
+This reverts commit 0a83f1a441d7aaadecb368c237b6ee70bd7b91d6.
+
+Building the Buildroot defconfig qemu_sparc_ss10_defconfig using
+gcc 8.4, 9.3 and 10 produce a broken rootfs that trigger illegal
+instruction messages.
+
+gcc 8.3, 9.2 are the latest working gcc version.
+git bisect between gcc 8.4 and 8.4 allowed to identify
+the commit that introcuce the regression.
+
+Reverting this patch allowed to produce a working rootfs.
+
+Signed-off-by: Romain Naour <romain.naour@gmail.com>
+Cc: Eric Botcazou <ebotcazou@gcc.gnu.org>
+---
+ gcc/config/sparc/sparc-protos.h | 1 -
+ gcc/config/sparc/sparc.c | 121 +++++++-----------
+ gcc/config/sparc/sparc.md | 5 +-
+ .../gcc.c-torture/compile/20191108-1.c | 14 --
+ gcc/testsuite/gcc.target/sparc/overflow-3.c | 2 +-
+ gcc/testsuite/gcc.target/sparc/overflow-4.c | 2 +-
+ gcc/testsuite/gcc.target/sparc/overflow-5.c | 2 +-
+ 7 files changed, 53 insertions(+), 94 deletions(-)
+ delete mode 100644 gcc/testsuite/gcc.c-torture/compile/20191108-1.c
+
+diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h
+index f525cd7a422..0d9f47af644 100644
+--- a/gcc/config/sparc/sparc-protos.h
++++ b/gcc/config/sparc/sparc-protos.h
+@@ -69,7 +69,6 @@ extern void sparc_split_reg_mem (rtx, rtx, machine_mode);
+ extern void sparc_split_mem_reg (rtx, rtx, machine_mode);
+ extern int sparc_split_reg_reg_legitimate (rtx, rtx);
+ extern void sparc_split_reg_reg (rtx, rtx, machine_mode);
+-extern const char *output_load_pcrel_sym (rtx *);
+ extern const char *output_ubranch (rtx, rtx_insn *);
+ extern const char *output_cbranch (rtx, rtx, int, int, int, rtx_insn *);
+ extern const char *output_return (rtx_insn *);
+diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
+index aefced85fe1..3ff6f9200f6 100644
+--- a/gcc/config/sparc/sparc.c
++++ b/gcc/config/sparc/sparc.c
+@@ -4192,6 +4192,13 @@ eligible_for_sibcall_delay (rtx_insn *trial)
+ static bool
+ sparc_cannot_force_const_mem (machine_mode mode, rtx x)
+ {
++ /* After IRA has run in PIC mode, it is too late to put anything into the
++ constant pool if the PIC register hasn't already been initialized. */
++ if ((lra_in_progress || reload_in_progress)
++ && flag_pic
++ && !crtl->uses_pic_offset_table)
++ return true;
++
+ switch (GET_CODE (x))
+ {
+ case CONST_INT:
+@@ -4227,11 +4234,9 @@ sparc_cannot_force_const_mem (machine_mode mode, rtx x)
+ }
+
+ /* Global Offset Table support. */
+-static GTY(()) rtx got_symbol_rtx = NULL_RTX;
+-static GTY(()) rtx got_register_rtx = NULL_RTX;
+ static GTY(()) rtx got_helper_rtx = NULL_RTX;
+-
+-static GTY(()) bool got_helper_needed = false;
++static GTY(()) rtx got_register_rtx = NULL_RTX;
++static GTY(()) rtx got_symbol_rtx = NULL_RTX;
+
+ /* Return the SYMBOL_REF for the Global Offset Table. */
+
+@@ -4244,6 +4249,27 @@ sparc_got (void)
+ return got_symbol_rtx;
+ }
+
++#ifdef HAVE_GAS_HIDDEN
++# define USE_HIDDEN_LINKONCE 1
++#else
++# define USE_HIDDEN_LINKONCE 0
++#endif
++
++static void
++get_pc_thunk_name (char name[32], unsigned int regno)
++{
++ const char *reg_name = reg_names[regno];
++
++ /* Skip the leading '%' as that cannot be used in a
++ symbol name. */
++ reg_name += 1;
++
++ if (USE_HIDDEN_LINKONCE)
++ sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
++ else
++ ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
++}
++
+ /* Wrapper around the load_pcrel_sym{si,di} patterns. */
+
+ static rtx
+@@ -4263,78 +4289,30 @@ gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2)
+ return insn;
+ }
+
+-/* Output the load_pcrel_sym{si,di} patterns. */
+-
+-const char *
+-output_load_pcrel_sym (rtx *operands)
+-{
+- if (flag_delayed_branch)
+- {
+- output_asm_insn ("sethi\t%%hi(%a1-4), %0", operands);
+- output_asm_insn ("call\t%a2", operands);
+- output_asm_insn (" add\t%0, %%lo(%a1+4), %0", operands);
+- }
+- else
+- {
+- output_asm_insn ("sethi\t%%hi(%a1-8), %0", operands);
+- output_asm_insn ("add\t%0, %%lo(%a1-4), %0", operands);
+- output_asm_insn ("call\t%a2", operands);
+- output_asm_insn (" nop", NULL);
+- }
+-
+- if (operands[2] == got_helper_rtx)
+- got_helper_needed = true;
+-
+- return "";
+-}
+-
+-#ifdef HAVE_GAS_HIDDEN
+-# define USE_HIDDEN_LINKONCE 1
+-#else
+-# define USE_HIDDEN_LINKONCE 0
+-#endif
+-
+ /* Emit code to load the GOT register. */
+
+ void
+ load_got_register (void)
+ {
+- rtx insn;
++ if (!got_register_rtx)
++ got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
+
+ if (TARGET_VXWORKS_RTP)
+- {
+- if (!got_register_rtx)
+- got_register_rtx = pic_offset_table_rtx;
+-
+- insn = gen_vxworks_load_got ();
+- }
++ emit_insn (gen_vxworks_load_got ());
+ else
+ {
+- if (!got_register_rtx)
+- got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
+-
+ /* The GOT symbol is subject to a PC-relative relocation so we need a
+ helper function to add the PC value and thus get the final value. */
+ if (!got_helper_rtx)
+ {
+ char name[32];
+-
+- /* Skip the leading '%' as that cannot be used in a symbol name. */
+- if (USE_HIDDEN_LINKONCE)
+- sprintf (name, "__sparc_get_pc_thunk.%s",
+- reg_names[REGNO (got_register_rtx)] + 1);
+- else
+- ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC",
+- REGNO (got_register_rtx));
+-
++ get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
+ got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
+ }
+
+- insn
+- = gen_load_pcrel_sym (got_register_rtx, sparc_got (), got_helper_rtx);
++ emit_insn (gen_load_pcrel_sym (got_register_rtx, sparc_got (),
++ got_helper_rtx));
+ }
+-
+- emit_insn (insn);
+ }
+
+ /* Ensure that we are not using patterns that are not OK with PIC. */
+@@ -5499,7 +5477,7 @@ save_local_or_in_reg_p (unsigned int regno, int leaf_function)
+ return true;
+
+ /* GOT register (%l7) if needed. */
+- if (got_register_rtx && regno == REGNO (got_register_rtx))
++ if (regno == GLOBAL_OFFSET_TABLE_REGNUM && got_register_rtx)
+ return true;
+
+ /* If the function accesses prior frames, the frame pointer and the return
+@@ -12542,9 +12520,10 @@ static void
+ sparc_file_end (void)
+ {
+ /* If we need to emit the special GOT helper function, do so now. */
+- if (got_helper_needed)
++ if (got_helper_rtx)
+ {
+ const char *name = XSTR (got_helper_rtx, 0);
++ const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
+ #ifdef DWARF2_UNWIND_INFO
+ bool do_cfi;
+ #endif
+@@ -12581,22 +12560,17 @@ sparc_file_end (void)
+ #ifdef DWARF2_UNWIND_INFO
+ do_cfi = dwarf2out_do_cfi_asm ();
+ if (do_cfi)
+- output_asm_insn (".cfi_startproc", NULL);
++ fprintf (asm_out_file, "\t.cfi_startproc\n");
+ #endif
+ if (flag_delayed_branch)
+- {
+- output_asm_insn ("jmp\t%%o7+8", NULL);
+- output_asm_insn (" add\t%%o7, %0, %0", &got_register_rtx);
+- }
++ fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
++ reg_name, reg_name);
+ else
+- {
+- output_asm_insn ("add\t%%o7, %0, %0", &got_register_rtx);
+- output_asm_insn ("jmp\t%%o7+8", NULL);
+- output_asm_insn (" nop", NULL);
+- }
++ fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
++ reg_name, reg_name);
+ #ifdef DWARF2_UNWIND_INFO
+ if (do_cfi)
+- output_asm_insn (".cfi_endproc", NULL);
++ fprintf (asm_out_file, "\t.cfi_endproc\n");
+ #endif
+ }
+
+@@ -13091,10 +13065,7 @@ sparc_init_pic_reg (void)
+ edge entry_edge;
+ rtx_insn *seq;
+
+- /* In PIC mode, we need to always initialize the PIC register if optimization
+- is enabled, because we are called from IRA and LRA may later force things
+- to the constant pool for optimization purposes. */
+- if (!flag_pic || (!crtl->uses_pic_offset_table && !optimize))
++ if (!crtl->uses_pic_offset_table)
+ return;
+
+ start_sequence ();
+diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
+index 231c0d84778..899804b80ae 100644
+--- a/gcc/config/sparc/sparc.md
++++ b/gcc/config/sparc/sparc.md
+@@ -1604,7 +1604,10 @@
+ (clobber (reg:P O7_REG))]
+ "REGNO (operands[0]) == INTVAL (operands[3])"
+ {
+- return output_load_pcrel_sym (operands);
++ if (flag_delayed_branch)
++ return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0";
++ else
++ return "sethi\t%%hi(%a1-8), %0\n\tadd\t%0, %%lo(%a1-4), %0\n\tcall\t%a2\n\t nop";
+ }
+ [(set (attr "type") (const_string "multi"))
+ (set (attr "length")
+diff --git a/gcc/testsuite/gcc.c-torture/compile/20191108-1.c b/gcc/testsuite/gcc.c-torture/compile/20191108-1.c
+deleted file mode 100644
+index 7929751bb06..00000000000
+--- a/gcc/testsuite/gcc.c-torture/compile/20191108-1.c
++++ /dev/null
+@@ -1,14 +0,0 @@
+-/* PR target/92095 */
+-/* Testcase by Sergei Trofimovich <slyfox@inbox.ru> */
+-
+-typedef union {
+- double a;
+- int b[2];
+-} c;
+-
+-double d(int e)
+-{
+- c f;
+- (&f)->b[0] = 15728640;
+- return e ? -(&f)->a : (&f)->a;
+-}
+diff --git a/gcc/testsuite/gcc.target/sparc/overflow-3.c b/gcc/testsuite/gcc.target/sparc/overflow-3.c
+index 52d6ab2b688..86dddfb09e6 100644
+--- a/gcc/testsuite/gcc.target/sparc/overflow-3.c
++++ b/gcc/testsuite/gcc.target/sparc/overflow-3.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+-/* { dg-options "-O -fno-pie" } */
++/* { dg-options "-O" } */
+
+ #include <stdbool.h>
+ #include <stdint.h>
+diff --git a/gcc/testsuite/gcc.target/sparc/overflow-4.c b/gcc/testsuite/gcc.target/sparc/overflow-4.c
+index c6121b958c3..019feee335c 100644
+--- a/gcc/testsuite/gcc.target/sparc/overflow-4.c
++++ b/gcc/testsuite/gcc.target/sparc/overflow-4.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+-/* { dg-options "-O -fno-pie -mno-vis3 -mno-vis4" } */
++/* { dg-options "-O -mno-vis3 -mno-vis4" } */
+
+ #include <stdbool.h>
+ #include <stdint.h>
+diff --git a/gcc/testsuite/gcc.target/sparc/overflow-5.c b/gcc/testsuite/gcc.target/sparc/overflow-5.c
+index f00283f6e7b..67d4ac38095 100644
+--- a/gcc/testsuite/gcc.target/sparc/overflow-5.c
++++ b/gcc/testsuite/gcc.target/sparc/overflow-5.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+-/* { dg-options "-O -fno-pie -mvis3" } */
++/* { dg-options "-O -mvis3" } */
+
+ #include <stdbool.h>
+ #include <stdint.h>
+--
+2.25.4
+
diff --git a/package/gcc/7.5.0/0001-uclibc-conf.patch b/package/gcc/7.5.0/0001-uclibc-conf.patch
deleted file mode 100644
index 29c5c010ed..0000000000
--- a/package/gcc/7.5.0/0001-uclibc-conf.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 0ff63500a600b758cd88ebcd048d7150df9ac881 Mon Sep 17 00:00:00 2001
-From: Romain Naour <romain.naour@gmail.com>
-Date: Tue, 2 May 2017 22:36:15 +0200
-Subject: [PATCH] uclibc-conf
-
-[Romain: convert to git patch]
-Signed-off-by: Romain Naour <romain.naour@gmail.com>
----
- contrib/regression/objs-gcc.sh | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/contrib/regression/objs-gcc.sh b/contrib/regression/objs-gcc.sh
-index 60b0497fea2..6dc7eadff36 100755
---- a/contrib/regression/objs-gcc.sh
-+++ b/contrib/regression/objs-gcc.sh
-@@ -106,6 +106,10 @@ if [ $H_REAL_TARGET = $H_REAL_HOST -a $H_REAL_TARGET = i686-pc-linux-gnu ]
- then
- make all-gdb all-dejagnu all-ld || exit 1
- make install-gdb install-dejagnu install-ld || exit 1
-+elif [ $H_REAL_TARGET = $H_REAL_HOST -a $H_REAL_TARGET = i686-pc-linux-uclibc ]
-+ then
-+ make all-gdb all-dejagnu all-ld || exit 1
-+ make install-gdb install-dejagnu install-ld || exit 1
- elif [ $H_REAL_TARGET = $H_REAL_HOST ] ; then
- make bootstrap || exit 1
- make install || exit 1
---
-2.21.0
-
diff --git a/package/gcc/7.5.0/0002-arm-softfloat-libgcc.patch b/package/gcc/7.5.0/0002-arm-softfloat-libgcc.patch
deleted file mode 100644
index c2c3450310..0000000000
--- a/package/gcc/7.5.0/0002-arm-softfloat-libgcc.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 1d0a47a72a1357e4a298d611bd2499e1b72c6f86 Mon Sep 17 00:00:00 2001
-From: Romain Naour <romain.naour@gmail.com>
-Date: Tue, 2 May 2017 22:46:18 +0200
-Subject: [PATCH] arm softfloat libgcc
-
-[Romain: convert to git patch]
-Signed-off-by: Romain Naour <romain.naour@gmail.com>
----
- gcc/config/arm/linux-elf.h | 2 +-
- libgcc/config/arm/t-linux | 7 ++++++-
- 2 files changed, 7 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/config/arm/linux-elf.h b/gcc/config/arm/linux-elf.h
-index 3d62367ae68..dad0b97d39f 100644
---- a/gcc/config/arm/linux-elf.h
-+++ b/gcc/config/arm/linux-elf.h
-@@ -58,7 +58,7 @@
- %{shared:-lc} \
- %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
-
--#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
-+#define LIBGCC_SPEC "-lgcc"
-
- #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
-
-diff --git a/libgcc/config/arm/t-linux b/libgcc/config/arm/t-linux
-index 3d520decafb..e7bc042d4e4 100644
---- a/libgcc/config/arm/t-linux
-+++ b/libgcc/config/arm/t-linux
-@@ -1,6 +1,11 @@
- LIB1ASMSRC = arm/lib1funcs.S
- LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \
-- _ctzsi2 _arm_addsubdf3 _arm_addsubsf3
-+ _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \
-+ _arm_addsubdf3 _arm_addsubsf3 \
-+ _arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \
-+ _arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \
-+ _arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \
-+ _arm_fixsfsi _arm_fixunssfsi
-
- # Just for these, we omit the frame pointer since it makes such a big
- # difference.
---
-2.21.0
-
diff --git a/package/gcc/7.5.0/0003-cilk-fix-build-without-wchar.patch b/package/gcc/7.5.0/0003-cilk-fix-build-without-wchar.patch
deleted file mode 100644
index 7821d06024..0000000000
--- a/package/gcc/7.5.0/0003-cilk-fix-build-without-wchar.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From a605662776a3bd50ebbb84509958cb42f44ec998 Mon Sep 17 00:00:00 2001
-From: Peter Korsgaard <peter@korsgaard.com>
-Date: Tue, 2 May 2017 23:21:46 +0200
-Subject: [PATCH] cilk: fix build without wchar
-
-When building against uClibc with wchar support disabled, WCHAR_MIN and
-WCHAR_MAX are not defined leading to compilation errors.
-
-Fix it by only including the wchar code if available.
-
-Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
-[Romain: convert to git patch]
-Signed-off-by: Romain Naour <romain.naour@gmail.com>
----
- libcilkrts/include/cilk/reducer_min_max.h | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/libcilkrts/include/cilk/reducer_min_max.h b/libcilkrts/include/cilk/reducer_min_max.h
-index 641aa823901..4f8e0102b90 100644
---- a/libcilkrts/include/cilk/reducer_min_max.h
-+++ b/libcilkrts/include/cilk/reducer_min_max.h
-@@ -3289,7 +3289,9 @@ __CILKRTS_BEGIN_EXTERN_C
- CILK_C_REDUCER_MAX_INSTANCE(char, char, CHAR_MIN)
- CILK_C_REDUCER_MAX_INSTANCE(unsigned char, uchar, 0)
- CILK_C_REDUCER_MAX_INSTANCE(signed char, schar, SCHAR_MIN)
-+#ifdef WCHAR_MIN
- CILK_C_REDUCER_MAX_INSTANCE(wchar_t, wchar_t, WCHAR_MIN)
-+#endif
- CILK_C_REDUCER_MAX_INSTANCE(short, short, SHRT_MIN)
- CILK_C_REDUCER_MAX_INSTANCE(unsigned short, ushort, 0)
- CILK_C_REDUCER_MAX_INSTANCE(int, int, INT_MIN)
-@@ -3441,7 +3443,9 @@ __CILKRTS_BEGIN_EXTERN_C
- CILK_C_REDUCER_MAX_INDEX_INSTANCE(char, char, CHAR_MIN)
- CILK_C_REDUCER_MAX_INDEX_INSTANCE(unsigned char, uchar, 0)
- CILK_C_REDUCER_MAX_INDEX_INSTANCE(signed char, schar, SCHAR_MIN)
-+#ifdef WCHAR_MIN
- CILK_C_REDUCER_MAX_INDEX_INSTANCE(wchar_t, wchar_t, WCHAR_MIN)
-+#endif
- CILK_C_REDUCER_MAX_INDEX_INSTANCE(short, short, SHRT_MIN)
- CILK_C_REDUCER_MAX_INDEX_INSTANCE(unsigned short, ushort, 0)
- CILK_C_REDUCER_MAX_INDEX_INSTANCE(int, int, INT_MIN)
-@@ -3567,7 +3571,9 @@ __CILKRTS_BEGIN_EXTERN_C
- CILK_C_REDUCER_MIN_INSTANCE(char, char, CHAR_MAX)
- CILK_C_REDUCER_MIN_INSTANCE(unsigned char, uchar, CHAR_MAX)
- CILK_C_REDUCER_MIN_INSTANCE(signed char, schar, SCHAR_MAX)
-+#ifdef WCHAR_MAX
- CILK_C_REDUCER_MIN_INSTANCE(wchar_t, wchar_t, WCHAR_MAX)
-+#endif
- CILK_C_REDUCER_MIN_INSTANCE(short, short, SHRT_MAX)
- CILK_C_REDUCER_MIN_INSTANCE(unsigned short, ushort, USHRT_MAX)
- CILK_C_REDUCER_MIN_INSTANCE(int, int, INT_MAX)
-@@ -3719,7 +3725,9 @@ __CILKRTS_BEGIN_EXTERN_C
- CILK_C_REDUCER_MIN_INDEX_INSTANCE(char, char, CHAR_MAX)
- CILK_C_REDUCER_MIN_INDEX_INSTANCE(unsigned char, uchar, CHAR_MAX)
- CILK_C_REDUCER_MIN_INDEX_INSTANCE(signed char, schar, SCHAR_MAX)
-+#ifdef WCHAR_MAX
- CILK_C_REDUCER_MIN_INDEX_INSTANCE(wchar_t, wchar_t, WCHAR_MAX)
-+#endif
- CILK_C_REDUCER_MIN_INDEX_INSTANCE(short, short, SHRT_MAX)
- CILK_C_REDUCER_MIN_INDEX_INSTANCE(unsigned short, ushort, USHRT_MAX)
- CILK_C_REDUCER_MIN_INDEX_INSTANCE(int, int, INT_MAX)
---
-2.21.0
-
diff --git a/package/gcc/7.5.0/0004-Revert-2016-01-21-Ajit-Agarwal-ajitkum-xilinx.com.patch b/package/gcc/7.5.0/0004-Revert-2016-01-21-Ajit-Agarwal-ajitkum-xilinx.com.patch
deleted file mode 100644
index 0ae6876ee6..0000000000
--- a/package/gcc/7.5.0/0004-Revert-2016-01-21-Ajit-Agarwal-ajitkum-xilinx.com.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 01fb9550fd858e441c3c2f358318af6e28e56181 Mon Sep 17 00:00:00 2001
-From: eager <eager@138bc75d-0d04-0410-961f-82ee72b054a4>
-Date: Sat, 27 May 2017 18:29:40 +0000
-Subject: [PATCH] Revert: 2016-01-21 Ajit Agarwal <ajitkum@xilinx.com>
-
- See https://gcc.gnu.org/ml/gcc/2017-05/msg00221.html.
-
- * config/microblaze/microblaze.h
- (FIXED_REGISTERS): Update in macro.
- (CALL_USED_REGISTERS): Update in macro.
-
-git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248540 138bc75d-0d04-0410-961f-82ee72b054a4
-Signed-off-by: Waldemar Brodkorb <wbx@openadk.org>
-Signed-off-by: Romain Naour <romain.naour@gmail.com>
----
- gcc/config/microblaze/microblaze.h | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 66e4ef5c3db..2c9ece1d6c6 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -269,14 +269,14 @@ extern enum pipeline_type microblaze_pipe;
- #define FIXED_REGISTERS \
- { \
- 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
-- 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-+ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 1, 1, 1, 1 \
- }
-
- #define CALL_USED_REGISTERS \
- { \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-- 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-+ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 1, 1, 1, 1 \
- }
- #define GP_REG_FIRST 0
---
-2.21.0
-
diff --git a/package/gcc/7.5.0/0005-PR-target-81497-Fix-arm_acle.h-for-C.patch b/package/gcc/7.5.0/0005-PR-target-81497-Fix-arm_acle.h-for-C.patch
deleted file mode 100644
index 0c7ab36770..0000000000
--- a/package/gcc/7.5.0/0005-PR-target-81497-Fix-arm_acle.h-for-C.patch
+++ /dev/null
@@ -1,323 +0,0 @@
-From f1c05207166a16d0a6242f2fa642adc439f835a8 Mon Sep 17 00:00:00 2001
-From: ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4>
-Date: Tue, 5 Jun 2018 09:50:16 +0000
-Subject: [PATCH] PR target/81497: Fix arm_acle.h for C++
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-When trying to compile something with arm_acle.h using G++ we get a number of nasty errors:
-arm_acle.h:48:49: error: invalid conversion from ‘const void*’ to ‘const int*’ [-fpermissive]
- return __builtin_arm_ldc (__coproc, __CRd, __p);
-
-This is because the intrinsics that are supposed to be void return the "result" of their builtin,
-which is void. C lets that slide but C++ complains.
-
-After fixing that we run into further errors:
-arm_acle.h:48:46: error: invalid conversion from 'const void*' to 'const int*' [-fpermissive]
- return __builtin_arm_ldc (__coproc, __CRd, __p);
- ^~~
-Because the pointer arguments in these intrinsics are void pointers but the builtin
-expects int pointers. So this patch introduces new qualifiers for void pointers and their
-const-qualified versions and uses that in the specification of these intrinsics.
-
-This gives us the opportunity of creating an arm subdirectory in g++.dg and inaugurates it
-with the first arm-specific C++ tests (in that directory).
-
- PR target/81497
- * config/arm/arm-builtins.c (arm_type_qualifiers): Add
- qualifier_void_pointer and qualifier_const_void_pointer.
- (arm_ldc_qualifiers, arm_stc_qualifiers): Use the above.
- (arm_init_builtins): Handle the above.
- * config/arm/arm_acle.h (__arm_cdp, __arm_ldc, __arm_ldcl, __arm_stc,
- __arm_stcl, __arm_mcr, __arm_cdp2, __arm_ldc2, __arm_ldcl2, __arm_stc2,
- __arm_stcl2,__arm_mcr2, __arm_mcrr, __arm_mcrr2): Remove return for
- void intrinsics.
-
- * g++.target/arm/arm.exp: New file.
- * g++.target/arm/pr81497.C: Likewise.
-
-git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@261191 138bc75d-0d04-0410-961f-82ee72b054a4
-Upstream-Status: Merged (gcc-8-branch)
-Signed-off-by: Gaël PORTAY <gael.portay@savoirfairelinux.com>
-[gportay: drop gcc/{,testsuite/}ChangeLog changes]
-Signed-off-by: Romain Naour <romain.naour@gmail.com>
----
- gcc/config/arm/arm-builtins.c | 42 +++++++++++++---------
- gcc/config/arm/arm_acle.h | 28 +++++++--------
- gcc/testsuite/g++.target/arm/arm.exp | 50 ++++++++++++++++++++++++++
- gcc/testsuite/g++.target/arm/pr81497.C | 9 +++++
- 4 files changed, 99 insertions(+), 30 deletions(-)
- create mode 100644 gcc/testsuite/g++.target/arm/arm.exp
- create mode 100644 gcc/testsuite/g++.target/arm/pr81497.C
-
-diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
-index d3b67184362..dd56f13251f 100644
---- a/gcc/config/arm/arm-builtins.c
-+++ b/gcc/config/arm/arm-builtins.c
-@@ -75,7 +75,11 @@ enum arm_type_qualifiers
- /* Lane indices - must be within range of previous argument = a vector. */
- qualifier_lane_index = 0x200,
- /* Lane indices for single lane structure loads and stores. */
-- qualifier_struct_load_store_lane_index = 0x400
-+ qualifier_struct_load_store_lane_index = 0x400,
-+ /* A void pointer. */
-+ qualifier_void_pointer = 0x800,
-+ /* A const void pointer. */
-+ qualifier_const_void_pointer = 0x802
- };
-
- /* The qualifier_internal allows generation of a unary builtin from
-@@ -185,7 +189,7 @@ arm_cdp_qualifiers[SIMD_MAX_BUILTIN_ARGS]
- static enum arm_type_qualifiers
- arm_ldc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
- = { qualifier_void, qualifier_unsigned_immediate,
-- qualifier_unsigned_immediate, qualifier_const_pointer };
-+ qualifier_unsigned_immediate, qualifier_const_void_pointer };
- #define LDC_QUALIFIERS \
- (arm_ldc_qualifiers)
-
-@@ -193,7 +197,7 @@ arm_ldc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
- static enum arm_type_qualifiers
- arm_stc_qualifiers[SIMD_MAX_BUILTIN_ARGS]
- = { qualifier_void, qualifier_unsigned_immediate,
-- qualifier_unsigned_immediate, qualifier_pointer };
-+ qualifier_unsigned_immediate, qualifier_void_pointer };
- #define STC_QUALIFIERS \
- (arm_stc_qualifiers)
-
-@@ -1079,19 +1083,25 @@ arm_init_builtin (unsigned int fcode, arm_builtin_datum *d,
- if (qualifiers & qualifier_pointer && VECTOR_MODE_P (op_mode))
- op_mode = GET_MODE_INNER (op_mode);
-
-- eltype = arm_simd_builtin_type
-- (op_mode,
-- (qualifiers & qualifier_unsigned) != 0,
-- (qualifiers & qualifier_poly) != 0);
-- gcc_assert (eltype != NULL);
--
-- /* Add qualifiers. */
-- if (qualifiers & qualifier_const)
-- eltype = build_qualified_type (eltype, TYPE_QUAL_CONST);
--
-- if (qualifiers & qualifier_pointer)
-- eltype = build_pointer_type (eltype);
--
-+ /* For void pointers we already have nodes constructed by the midend. */
-+ if (qualifiers & qualifier_void_pointer)
-+ eltype = qualifiers & qualifier_const
-+ ? const_ptr_type_node : ptr_type_node;
-+ else
-+ {
-+ eltype
-+ = arm_simd_builtin_type (op_mode,
-+ (qualifiers & qualifier_unsigned) != 0,
-+ (qualifiers & qualifier_poly) != 0);
-+ gcc_assert (eltype != NULL);
-+
-+ /* Add qualifiers. */
-+ if (qualifiers & qualifier_const)
-+ eltype = build_qualified_type (eltype, TYPE_QUAL_CONST);
-+
-+ if (qualifiers & qualifier_pointer)
-+ eltype = build_pointer_type (eltype);
-+ }
- /* If we have reached arg_num == 0, we are at a non-void
- return type. Otherwise, we are still processing
- arguments. */
-diff --git a/gcc/config/arm/arm_acle.h b/gcc/config/arm/arm_acle.h
-index 972e28edb86..69c29df4313 100644
---- a/gcc/config/arm/arm_acle.h
-+++ b/gcc/config/arm/arm_acle.h
-@@ -38,35 +38,35 @@ __arm_cdp (const unsigned int __coproc, const unsigned int __opc1,
- const unsigned int __CRd, const unsigned int __CRn,
- const unsigned int __CRm, const unsigned int __opc2)
- {
-- return __builtin_arm_cdp (__coproc, __opc1, __CRd, __CRn, __CRm, __opc2);
-+ __builtin_arm_cdp (__coproc, __opc1, __CRd, __CRn, __CRm, __opc2);
- }
-
- __extension__ static __inline void __attribute__ ((__always_inline__))
- __arm_ldc (const unsigned int __coproc, const unsigned int __CRd,
- const void * __p)
- {
-- return __builtin_arm_ldc (__coproc, __CRd, __p);
-+ __builtin_arm_ldc (__coproc, __CRd, __p);
- }
-
- __extension__ static __inline void __attribute__ ((__always_inline__))
- __arm_ldcl (const unsigned int __coproc, const unsigned int __CRd,
- const void * __p)
- {
-- return __builtin_arm_ldcl (__coproc, __CRd, __p);
-+ __builtin_arm_ldcl (__coproc, __CRd, __p);
- }
-
- __extension__ static __inline void __attribute__ ((__always_inline__))
- __arm_stc (const unsigned int __coproc, const unsigned int __CRd,
- void * __p)
- {
-- return __builtin_arm_stc (__coproc, __CRd, __p);
-+ __builtin_arm_stc (__coproc, __CRd, __p);
- }
-
- __extension__ static __inline void __attribute__ ((__always_inline__))
- __arm_stcl (const unsigned int __coproc, const unsigned int __CRd,
- void * __p)
- {
-- return __builtin_arm_stcl (__coproc, __CRd, __p);
-+ __builtin_arm_stcl (__coproc, __CRd, __p);
- }
-
- __extension__ static __inline void __attribute__ ((__always_inline__))
-@@ -74,7 +74,7 @@ __arm_mcr (const unsigned int __coproc, const unsigned int __opc1,
- uint32_t __value, const unsigned int __CRn, const unsigned int __CRm,
- const unsigned int __opc2)
- {
-- return __builtin_arm_mcr (__coproc, __opc1, __value, __CRn, __CRm, __opc2);
-+ __builtin_arm_mcr (__coproc, __opc1, __value, __CRn, __CRm, __opc2);
- }
-
- __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
-@@ -90,35 +90,35 @@ __arm_cdp2 (const unsigned int __coproc, const unsigned int __opc1,
- const unsigned int __CRd, const unsigned int __CRn,
- const unsigned int __CRm, const unsigned int __opc2)
- {
-- return __builtin_arm_cdp2 (__coproc, __opc1, __CRd, __CRn, __CRm, __opc2);
-+ __builtin_arm_cdp2 (__coproc, __opc1, __CRd, __CRn, __CRm, __opc2);
- }
-
- __extension__ static __inline void __attribute__ ((__always_inline__))
- __arm_ldc2 (const unsigned int __coproc, const unsigned int __CRd,
- const void * __p)
- {
-- return __builtin_arm_ldc2 (__coproc, __CRd, __p);
-+ __builtin_arm_ldc2 (__coproc, __CRd, __p);
- }
-
- __extension__ static __inline void __attribute__ ((__always_inline__))
- __arm_ldc2l (const unsigned int __coproc, const unsigned int __CRd,
- const void * __p)
- {
-- return __builtin_arm_ldc2l (__coproc, __CRd, __p);
-+ __builtin_arm_ldc2l (__coproc, __CRd, __p);
- }
-
- __extension__ static __inline void __attribute__ ((__always_inline__))
- __arm_stc2 (const unsigned int __coproc, const unsigned int __CRd,
- void * __p)
- {
-- return __builtin_arm_stc2 (__coproc, __CRd, __p);
-+ __builtin_arm_stc2 (__coproc, __CRd, __p);
- }
-
- __extension__ static __inline void __attribute__ ((__always_inline__))
- __arm_stc2l (const unsigned int __coproc, const unsigned int __CRd,
- void * __p)
- {
-- return __builtin_arm_stc2l (__coproc, __CRd, __p);
-+ __builtin_arm_stc2l (__coproc, __CRd, __p);
- }
-
- __extension__ static __inline void __attribute__ ((__always_inline__))
-@@ -126,7 +126,7 @@ __arm_mcr2 (const unsigned int __coproc, const unsigned int __opc1,
- uint32_t __value, const unsigned int __CRn,
- const unsigned int __CRm, const unsigned int __opc2)
- {
-- return __builtin_arm_mcr2 (__coproc, __opc1, __value, __CRn, __CRm, __opc2);
-+ __builtin_arm_mcr2 (__coproc, __opc1, __value, __CRn, __CRm, __opc2);
- }
-
- __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
-@@ -143,7 +143,7 @@ __extension__ static __inline void __attribute__ ((__always_inline__))
- __arm_mcrr (const unsigned int __coproc, const unsigned int __opc1,
- uint64_t __value, const unsigned int __CRm)
- {
-- return __builtin_arm_mcrr (__coproc, __opc1, __value, __CRm);
-+ __builtin_arm_mcrr (__coproc, __opc1, __value, __CRm);
- }
-
- __extension__ static __inline uint64_t __attribute__ ((__always_inline__))
-@@ -159,7 +159,7 @@ __extension__ static __inline void __attribute__ ((__always_inline__))
- __arm_mcrr2 (const unsigned int __coproc, const unsigned int __opc1,
- uint64_t __value, const unsigned int __CRm)
- {
-- return __builtin_arm_mcrr2 (__coproc, __opc1, __value, __CRm);
-+ __builtin_arm_mcrr2 (__coproc, __opc1, __value, __CRm);
- }
-
- __extension__ static __inline uint64_t __attribute__ ((__always_inline__))
-diff --git a/gcc/testsuite/g++.target/arm/arm.exp b/gcc/testsuite/g++.target/arm/arm.exp
-new file mode 100644
-index 00000000000..1a169d2f220
---- /dev/null
-+++ b/gcc/testsuite/g++.target/arm/arm.exp
-@@ -0,0 +1,50 @@
-+# Specific regression driver for arm.
-+# Copyright (C) 2009-2018 Free Software Foundation, Inc.
-+#
-+# This file is part of GCC.
-+#
-+# GCC is free software; you can redistribute it and/or modify it
-+# under the terms of the GNU General Public License as published by
-+# the Free Software Foundation; either version 3, or (at your option)
-+# any later version.
-+#
-+# GCC is distributed in the hope that it will be useful, but
-+# WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+# General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with GCC; see the file COPYING3. If not see
-+# <http://www.gnu.org/licenses/>. */
-+
-+# GCC testsuite that uses the `dg.exp' driver.
-+
-+# Exit immediately if this isn't an arm target.
-+if {![istarget arm*-*-*] } then {
-+ return
-+}
-+
-+# Load support procs.
-+load_lib g++-dg.exp
-+
-+global DEFAULT_CXXFLAGS
-+if ![info exists DEFAULT_CXXFLAGS] then {
-+ set DEFAULT_CXXFLAGS " -pedantic-errors"
-+}
-+
-+
-+global dg_runtest_extra_prunes
-+set dg_runtest_extra_prunes ""
-+lappend dg_runtest_extra_prunes "warning: switch -m(cpu|arch)=.* conflicts with -m(cpu|arch)=.* switch"
-+
-+# Initialize `dg'.
-+dg-init
-+
-+# Main loop.
-+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] \
-+ "" $DEFAULT_CXXFLAGS
-+
-+# All done.
-+set dg_runtest_extra_prunes ""
-+dg-finish
-+
-diff --git a/gcc/testsuite/g++.target/arm/pr81497.C b/gcc/testsuite/g++.target/arm/pr81497.C
-new file mode 100644
-index 00000000000..0519a3a3045
---- /dev/null
-+++ b/gcc/testsuite/g++.target/arm/pr81497.C
-@@ -0,0 +1,9 @@
-+/* { dg-do compile } */
-+/* { dg-require-effective-target arm_thumb2_ok } */
-+
-+#include <arm_acle.h>
-+
-+int main ()
-+{
-+ return 0;
-+}
---
-2.21.0
-
diff --git a/package/gcc/7.5.0/0006-gcc-define-_REENTRANT-for-RISC-V-when-pthread-is-pas.patch b/package/gcc/7.5.0/0006-gcc-define-_REENTRANT-for-RISC-V-when-pthread-is-pas.patch
deleted file mode 100644
index de0f453348..0000000000
--- a/package/gcc/7.5.0/0006-gcc-define-_REENTRANT-for-RISC-V-when-pthread-is-pas.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 1d78555bfc753039546ce5ca655dece67732e7bd Mon Sep 17 00:00:00 2001
-From: Mark Corbin <mark.corbin@embecosm.com>
-Date: Thu, 22 Nov 2018 12:19:11 +0000
-Subject: [PATCH] gcc: define _REENTRANT for RISC-V when -pthread is passed
-
-The detection of pthread support fails on RISC-V unless _REENTRANT
-is defined. Added the CPP_SPEC definition from gcc 8.1.0 to correct
-this.
-
-Signed-off-by: Mark Corbin <mark.corbin@embecosm.com>
-Signed-off-by: Romain Naour <romain.naour@gmail.com>
----
- gcc/config/riscv/linux.h | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
-index 4b2f7b6e1fd..b00d23ddfa0 100644
---- a/gcc/config/riscv/linux.h
-+++ b/gcc/config/riscv/linux.h
-@@ -47,6 +47,8 @@ along with GCC; see the file COPYING3. If not see
-
- #define ICACHE_FLUSH_FUNC "__riscv_flush_icache"
-
-+#define CPP_SPEC "%{pthread:-D_REENTRANT}"
-+
- #define LINK_SPEC "\
- -melf" XLEN_SPEC "lriscv \
- %{shared} \
---
-2.21.0
-
diff --git a/package/gcc/7.5.0/0007-xtensa-fix-PR-target-91880.patch b/package/gcc/7.5.0/0007-xtensa-fix-PR-target-91880.patch
deleted file mode 100644
index e75588bf4e..0000000000
--- a/package/gcc/7.5.0/0007-xtensa-fix-PR-target-91880.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 7c11710230921246156aecc20eb4b6ccaeaaa473 Mon Sep 17 00:00:00 2001
-From: Max Filippov <jcmvbkbc@gmail.com>
-Date: Tue, 24 Sep 2019 04:15:17 -0700
-Subject: [PATCH] xtensa: fix PR target/91880
-
-Xtensa hwloop_optimize segfaults when zero overhead loop is about to be
-inserted as the first instruction of the function.
-Insert zero overhead loop instruction into new basic block before the
-loop when basic block that precedes the loop is empty.
-
-2019-09-26 Max Filippov <jcmvbkbc@gmail.com>
-gcc/
- * config/xtensa/xtensa.c (hwloop_optimize): Insert zero overhead
- loop instruction into new basic block before the loop when basic
- block that precedes the loop is empty.
-
-Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
----
-Backported from: r276166
-
- gcc/config/xtensa/xtensa.c | 5 ++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
-index ee5612441e25..2527468d57db 100644
---- a/gcc/config/xtensa/xtensa.c
-+++ b/gcc/config/xtensa/xtensa.c
-@@ -4174,7 +4174,9 @@ hwloop_optimize (hwloop_info loop)
-
- seq = get_insns ();
-
-- if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1)
-+ entry_after = BB_END (entry_bb);
-+ if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1
-+ || !entry_after)
- {
- basic_block new_bb;
- edge e;
-@@ -4195,7 +4197,6 @@ hwloop_optimize (hwloop_info loop)
- }
- else
- {
-- entry_after = BB_END (entry_bb);
- while (DEBUG_INSN_P (entry_after)
- || (NOTE_P (entry_after)
- && NOTE_KIND (entry_after) != NOTE_INSN_BASIC_BLOCK
---
-2.11.0
-
diff --git a/package/gcc/8.4.0/0002-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch b/package/gcc/8.4.0/0002-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch
new file mode 100644
index 0000000000..ec2bf8835d
--- /dev/null
+++ b/package/gcc/8.4.0/0002-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch
@@ -0,0 +1,322 @@
+From bb9b71752267444b4360442b89129bfc0ae938d3 Mon Sep 17 00:00:00 2001
+From: Romain Naour <romain.naour@gmail.com>
+Date: Wed, 20 Jan 2021 23:06:07 +0100
+Subject: [PATCH] Revert "re PR target/92095 (internal error with -O1
+ -mcpu=niagara2 -fPIE)"
+
+This reverts commit 3fcce773f0f914c0499b130c6e9efa0e45ee54a0.
+
+Building the Buildroot defconfig qemu_sparc_ss10_defconfig using
+gcc 8.4, 9.3 and 10 produce a broken rootfs that trigger illegal
+instruction messages.
+
+gcc 8.3, 9.2 are the latest working gcc version.
+git bisect between gcc 8.4 and 8.4 allowed to identify
+the commit that introcuce the regression.
+
+Reverting this patch allowed to produce a working rootfs.
+
+Signed-off-by: Romain Naour <romain.naour@gmail.com>
+Cc: Eric Botcazou <ebotcazou@gcc.gnu.org>
+---
+ gcc/config/sparc/sparc-protos.h | 1 -
+ gcc/config/sparc/sparc.c | 121 +++++++-----------
+ gcc/config/sparc/sparc.md | 5 +-
+ .../gcc.c-torture/compile/20191108-1.c | 14 --
+ gcc/testsuite/gcc.target/sparc/overflow-3.c | 2 +-
+ gcc/testsuite/gcc.target/sparc/overflow-4.c | 2 +-
+ gcc/testsuite/gcc.target/sparc/overflow-5.c | 2 +-
+ 7 files changed, 53 insertions(+), 94 deletions(-)
+ delete mode 100644 gcc/testsuite/gcc.c-torture/compile/20191108-1.c
+
+diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h
+index b3f73c2f2bf..71a067e871c 100644
+--- a/gcc/config/sparc/sparc-protos.h
++++ b/gcc/config/sparc/sparc-protos.h
+@@ -69,7 +69,6 @@ extern void sparc_split_reg_mem (rtx, rtx, machine_mode);
+ extern void sparc_split_mem_reg (rtx, rtx, machine_mode);
+ extern int sparc_split_reg_reg_legitimate (rtx, rtx);
+ extern void sparc_split_reg_reg (rtx, rtx, machine_mode);
+-extern const char *output_load_pcrel_sym (rtx *);
+ extern const char *output_ubranch (rtx, rtx_insn *);
+ extern const char *output_cbranch (rtx, rtx, int, int, int, rtx_insn *);
+ extern const char *output_return (rtx_insn *);
+diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
+index 73032d33596..db1b428db90 100644
+--- a/gcc/config/sparc/sparc.c
++++ b/gcc/config/sparc/sparc.c
+@@ -4200,6 +4200,13 @@ eligible_for_sibcall_delay (rtx_insn *trial)
+ static bool
+ sparc_cannot_force_const_mem (machine_mode mode, rtx x)
+ {
++ /* After IRA has run in PIC mode, it is too late to put anything into the
++ constant pool if the PIC register hasn't already been initialized. */
++ if ((lra_in_progress || reload_in_progress)
++ && flag_pic
++ && !crtl->uses_pic_offset_table)
++ return true;
++
+ switch (GET_CODE (x))
+ {
+ case CONST_INT:
+@@ -4235,11 +4242,9 @@ sparc_cannot_force_const_mem (machine_mode mode, rtx x)
+ }
+
+ /* Global Offset Table support. */
+-static GTY(()) rtx got_symbol_rtx = NULL_RTX;
+-static GTY(()) rtx got_register_rtx = NULL_RTX;
+ static GTY(()) rtx got_helper_rtx = NULL_RTX;
+-
+-static GTY(()) bool got_helper_needed = false;
++static GTY(()) rtx got_register_rtx = NULL_RTX;
++static GTY(()) rtx got_symbol_rtx = NULL_RTX;
+
+ /* Return the SYMBOL_REF for the Global Offset Table. */
+
+@@ -4252,6 +4257,27 @@ sparc_got (void)
+ return got_symbol_rtx;
+ }
+
++#ifdef HAVE_GAS_HIDDEN
++# define USE_HIDDEN_LINKONCE 1
++#else
++# define USE_HIDDEN_LINKONCE 0
++#endif
++
++static void
++get_pc_thunk_name (char name[32], unsigned int regno)
++{
++ const char *reg_name = reg_names[regno];
++
++ /* Skip the leading '%' as that cannot be used in a
++ symbol name. */
++ reg_name += 1;
++
++ if (USE_HIDDEN_LINKONCE)
++ sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
++ else
++ ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
++}
++
+ /* Wrapper around the load_pcrel_sym{si,di} patterns. */
+
+ static rtx
+@@ -4271,78 +4297,30 @@ gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2)
+ return insn;
+ }
+
+-/* Output the load_pcrel_sym{si,di} patterns. */
+-
+-const char *
+-output_load_pcrel_sym (rtx *operands)
+-{
+- if (flag_delayed_branch)
+- {
+- output_asm_insn ("sethi\t%%hi(%a1-4), %0", operands);
+- output_asm_insn ("call\t%a2", operands);
+- output_asm_insn (" add\t%0, %%lo(%a1+4), %0", operands);
+- }
+- else
+- {
+- output_asm_insn ("sethi\t%%hi(%a1-8), %0", operands);
+- output_asm_insn ("add\t%0, %%lo(%a1-4), %0", operands);
+- output_asm_insn ("call\t%a2", operands);
+- output_asm_insn (" nop", NULL);
+- }
+-
+- if (operands[2] == got_helper_rtx)
+- got_helper_needed = true;
+-
+- return "";
+-}
+-
+-#ifdef HAVE_GAS_HIDDEN
+-# define USE_HIDDEN_LINKONCE 1
+-#else
+-# define USE_HIDDEN_LINKONCE 0
+-#endif
+-
+ /* Emit code to load the GOT register. */
+
+ void
+ load_got_register (void)
+ {
+- rtx insn;
++ if (!got_register_rtx)
++ got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
+
+ if (TARGET_VXWORKS_RTP)
+- {
+- if (!got_register_rtx)
+- got_register_rtx = pic_offset_table_rtx;
+-
+- insn = gen_vxworks_load_got ();
+- }
++ emit_insn (gen_vxworks_load_got ());
+ else
+ {
+- if (!got_register_rtx)
+- got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
+-
+ /* The GOT symbol is subject to a PC-relative relocation so we need a
+ helper function to add the PC value and thus get the final value. */
+ if (!got_helper_rtx)
+ {
+ char name[32];
+-
+- /* Skip the leading '%' as that cannot be used in a symbol name. */
+- if (USE_HIDDEN_LINKONCE)
+- sprintf (name, "__sparc_get_pc_thunk.%s",
+- reg_names[REGNO (got_register_rtx)] + 1);
+- else
+- ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC",
+- REGNO (got_register_rtx));
+-
++ get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
+ got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
+ }
+
+- insn
+- = gen_load_pcrel_sym (got_register_rtx, sparc_got (), got_helper_rtx);
++ emit_insn (gen_load_pcrel_sym (got_register_rtx, sparc_got (),
++ got_helper_rtx));
+ }
+-
+- emit_insn (insn);
+ }
+
+ /* Ensure that we are not using patterns that are not OK with PIC. */
+@@ -5494,7 +5472,7 @@ save_local_or_in_reg_p (unsigned int regno, int leaf_function)
+ return true;
+
+ /* GOT register (%l7) if needed. */
+- if (got_register_rtx && regno == REGNO (got_register_rtx))
++ if (regno == GLOBAL_OFFSET_TABLE_REGNUM && got_register_rtx)
+ return true;
+
+ /* If the function accesses prior frames, the frame pointer and the return
+@@ -12475,9 +12453,10 @@ static void
+ sparc_file_end (void)
+ {
+ /* If we need to emit the special GOT helper function, do so now. */
+- if (got_helper_needed)
++ if (got_helper_rtx)
+ {
+ const char *name = XSTR (got_helper_rtx, 0);
++ const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
+ #ifdef DWARF2_UNWIND_INFO
+ bool do_cfi;
+ #endif
+@@ -12514,22 +12493,17 @@ sparc_file_end (void)
+ #ifdef DWARF2_UNWIND_INFO
+ do_cfi = dwarf2out_do_cfi_asm ();
+ if (do_cfi)
+- output_asm_insn (".cfi_startproc", NULL);
++ fprintf (asm_out_file, "\t.cfi_startproc\n");
+ #endif
+ if (flag_delayed_branch)
+- {
+- output_asm_insn ("jmp\t%%o7+8", NULL);
+- output_asm_insn (" add\t%%o7, %0, %0", &got_register_rtx);
+- }
++ fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
++ reg_name, reg_name);
+ else
+- {
+- output_asm_insn ("add\t%%o7, %0, %0", &got_register_rtx);
+- output_asm_insn ("jmp\t%%o7+8", NULL);
+- output_asm_insn (" nop", NULL);
+- }
++ fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
++ reg_name, reg_name);
+ #ifdef DWARF2_UNWIND_INFO
+ if (do_cfi)
+- output_asm_insn (".cfi_endproc", NULL);
++ fprintf (asm_out_file, "\t.cfi_endproc\n");
+ #endif
+ }
+
+@@ -13035,10 +13009,7 @@ sparc_init_pic_reg (void)
+ edge entry_edge;
+ rtx_insn *seq;
+
+- /* In PIC mode, we need to always initialize the PIC register if optimization
+- is enabled, because we are called from IRA and LRA may later force things
+- to the constant pool for optimization purposes. */
+- if (!flag_pic || (!crtl->uses_pic_offset_table && !optimize))
++ if (!crtl->uses_pic_offset_table)
+ return;
+
+ start_sequence ();
+diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
+index 468e2cc5d3b..25134bd1148 100644
+--- a/gcc/config/sparc/sparc.md
++++ b/gcc/config/sparc/sparc.md
+@@ -1601,7 +1601,10 @@
+ (clobber (reg:P O7_REG))]
+ "REGNO (operands[0]) == INTVAL (operands[3])"
+ {
+- return output_load_pcrel_sym (operands);
++ if (flag_delayed_branch)
++ return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0";
++ else
++ return "sethi\t%%hi(%a1-8), %0\n\tadd\t%0, %%lo(%a1-4), %0\n\tcall\t%a2\n\t nop";
+ }
+ [(set (attr "type") (const_string "multi"))
+ (set (attr "length")
+diff --git a/gcc/testsuite/gcc.c-torture/compile/20191108-1.c b/gcc/testsuite/gcc.c-torture/compile/20191108-1.c
+deleted file mode 100644
+index 7929751bb06..00000000000
+--- a/gcc/testsuite/gcc.c-torture/compile/20191108-1.c
++++ /dev/null
+@@ -1,14 +0,0 @@
+-/* PR target/92095 */
+-/* Testcase by Sergei Trofimovich <slyfox@inbox.ru> */
+-
+-typedef union {
+- double a;
+- int b[2];
+-} c;
+-
+-double d(int e)
+-{
+- c f;
+- (&f)->b[0] = 15728640;
+- return e ? -(&f)->a : (&f)->a;
+-}
+diff --git a/gcc/testsuite/gcc.target/sparc/overflow-3.c b/gcc/testsuite/gcc.target/sparc/overflow-3.c
+index 18253bb6e5e..8cb24f52f7b 100644
+--- a/gcc/testsuite/gcc.target/sparc/overflow-3.c
++++ b/gcc/testsuite/gcc.target/sparc/overflow-3.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O -fno-pie" } */
++/* { dg-options "-O" } */
+ /* { dg-require-effective-target lp64 } */
+
+ #include <stdbool.h>
+diff --git a/gcc/testsuite/gcc.target/sparc/overflow-4.c b/gcc/testsuite/gcc.target/sparc/overflow-4.c
+index fb30877efb9..868edea2b9e 100644
+--- a/gcc/testsuite/gcc.target/sparc/overflow-4.c
++++ b/gcc/testsuite/gcc.target/sparc/overflow-4.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O -fno-pie -mno-vis3" } */
++/* { dg-options "-O -mno-vis3" } */
+ /* { dg-require-effective-target lp64 } */
+
+ #include <stdbool.h>
+diff --git a/gcc/testsuite/gcc.target/sparc/overflow-5.c b/gcc/testsuite/gcc.target/sparc/overflow-5.c
+index 509d957715d..501ce04f7a1 100644
+--- a/gcc/testsuite/gcc.target/sparc/overflow-5.c
++++ b/gcc/testsuite/gcc.target/sparc/overflow-5.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O -fno-pie -mvis3" } */
++/* { dg-options "-O -mvis3" } */
+ /* { dg-require-effective-target lp64 } */
+
+ #include <stdbool.h>
+--
+2.25.4
+
diff --git a/package/gcc/9.3.0/0005-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch b/package/gcc/9.3.0/0005-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch
new file mode 100644
index 0000000000..8ed281e981
--- /dev/null
+++ b/package/gcc/9.3.0/0005-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch
@@ -0,0 +1,325 @@
+From 0d7fe4806d9dce76367c193d5199df6a2b98009f Mon Sep 17 00:00:00 2001
+From: Romain Naour <romain.naour@gmail.com>
+Date: Wed, 20 Jan 2021 23:22:16 +0100
+Subject: [PATCH] Revert "re PR target/92095 (internal error with -O1
+ -mcpu=niagara2 -fPIE)"
+
+This reverts commit 6bf2990842388101897b6f465524cbc295ee8cf9.
+
+Building the Buildroot defconfig qemu_sparc_ss10_defconfig using
+gcc 8.4, 9.3 and 10 produce a broken rootfs that trigger illegal
+instruction messages.
+
+gcc 8.3, 9.2 are the latest working gcc version.
+git bisect between gcc 8.4 and 8.4 allowed to identify
+the commit that introcuce the regression.
+
+Reverting this patch allowed to produce a working rootfs.
+
+Signed-off-by: Romain Naour <romain.naour@gmail.com>
+Cc: Eric Botcazou <ebotcazou@gcc.gnu.org>
+---
+ gcc/config/sparc/sparc-protos.h | 1 -
+ gcc/config/sparc/sparc.c | 121 +++++++-----------
+ gcc/config/sparc/sparc.md | 5 +-
+ .../gcc.c-torture/compile/20191108-1.c | 14 --
+ gcc/testsuite/gcc.target/sparc/overflow-3.c | 2 +-
+ gcc/testsuite/gcc.target/sparc/overflow-4.c | 2 +-
+ gcc/testsuite/gcc.target/sparc/overflow-5.c | 2 +-
+ 7 files changed, 53 insertions(+), 94 deletions(-)
+ delete mode 100644 gcc/testsuite/gcc.c-torture/compile/20191108-1.c
+
+diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h
+index ef1adb69ede..9bdae7b9faa 100644
+--- a/gcc/config/sparc/sparc-protos.h
++++ b/gcc/config/sparc/sparc-protos.h
+@@ -69,7 +69,6 @@ extern void sparc_split_reg_mem (rtx, rtx, machine_mode);
+ extern void sparc_split_mem_reg (rtx, rtx, machine_mode);
+ extern int sparc_split_reg_reg_legitimate (rtx, rtx);
+ extern void sparc_split_reg_reg (rtx, rtx, machine_mode);
+-extern const char *output_load_pcrel_sym (rtx *);
+ extern const char *output_ubranch (rtx, rtx_insn *);
+ extern const char *output_cbranch (rtx, rtx, int, int, int, rtx_insn *);
+ extern const char *output_return (rtx_insn *);
+diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
+index a993aab7639..2974d174e93 100644
+--- a/gcc/config/sparc/sparc.c
++++ b/gcc/config/sparc/sparc.c
+@@ -4205,6 +4205,13 @@ eligible_for_sibcall_delay (rtx_insn *trial)
+ static bool
+ sparc_cannot_force_const_mem (machine_mode mode, rtx x)
+ {
++ /* After IRA has run in PIC mode, it is too late to put anything into the
++ constant pool if the PIC register hasn't already been initialized. */
++ if ((lra_in_progress || reload_in_progress)
++ && flag_pic
++ && !crtl->uses_pic_offset_table)
++ return true;
++
+ switch (GET_CODE (x))
+ {
+ case CONST_INT:
+@@ -4240,11 +4247,9 @@ sparc_cannot_force_const_mem (machine_mode mode, rtx x)
+ }
+
+ /* Global Offset Table support. */
+-static GTY(()) rtx got_symbol_rtx = NULL_RTX;
+-static GTY(()) rtx got_register_rtx = NULL_RTX;
+ static GTY(()) rtx got_helper_rtx = NULL_RTX;
+-
+-static GTY(()) bool got_helper_needed = false;
++static GTY(()) rtx got_register_rtx = NULL_RTX;
++static GTY(()) rtx got_symbol_rtx = NULL_RTX;
+
+ /* Return the SYMBOL_REF for the Global Offset Table. */
+
+@@ -4257,6 +4262,27 @@ sparc_got (void)
+ return got_symbol_rtx;
+ }
+
++#ifdef HAVE_GAS_HIDDEN
++# define USE_HIDDEN_LINKONCE 1
++#else
++# define USE_HIDDEN_LINKONCE 0
++#endif
++
++static void
++get_pc_thunk_name (char name[32], unsigned int regno)
++{
++ const char *reg_name = reg_names[regno];
++
++ /* Skip the leading '%' as that cannot be used in a
++ symbol name. */
++ reg_name += 1;
++
++ if (USE_HIDDEN_LINKONCE)
++ sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
++ else
++ ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
++}
++
+ /* Wrapper around the load_pcrel_sym{si,di} patterns. */
+
+ static rtx
+@@ -4276,78 +4302,30 @@ gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2)
+ return insn;
+ }
+
+-/* Output the load_pcrel_sym{si,di} patterns. */
+-
+-const char *
+-output_load_pcrel_sym (rtx *operands)
+-{
+- if (flag_delayed_branch)
+- {
+- output_asm_insn ("sethi\t%%hi(%a1-4), %0", operands);
+- output_asm_insn ("call\t%a2", operands);
+- output_asm_insn (" add\t%0, %%lo(%a1+4), %0", operands);
+- }
+- else
+- {
+- output_asm_insn ("sethi\t%%hi(%a1-8), %0", operands);
+- output_asm_insn ("add\t%0, %%lo(%a1-4), %0", operands);
+- output_asm_insn ("call\t%a2", operands);
+- output_asm_insn (" nop", NULL);
+- }
+-
+- if (operands[2] == got_helper_rtx)
+- got_helper_needed = true;
+-
+- return "";
+-}
+-
+-#ifdef HAVE_GAS_HIDDEN
+-# define USE_HIDDEN_LINKONCE 1
+-#else
+-# define USE_HIDDEN_LINKONCE 0
+-#endif
+-
+ /* Emit code to load the GOT register. */
+
+ void
+ load_got_register (void)
+ {
+- rtx insn;
++ if (!got_register_rtx)
++ got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
+
+ if (TARGET_VXWORKS_RTP)
+- {
+- if (!got_register_rtx)
+- got_register_rtx = pic_offset_table_rtx;
+-
+- insn = gen_vxworks_load_got ();
+- }
++ emit_insn (gen_vxworks_load_got ());
+ else
+ {
+- if (!got_register_rtx)
+- got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
+-
+ /* The GOT symbol is subject to a PC-relative relocation so we need a
+ helper function to add the PC value and thus get the final value. */
+ if (!got_helper_rtx)
+ {
+ char name[32];
+-
+- /* Skip the leading '%' as that cannot be used in a symbol name. */
+- if (USE_HIDDEN_LINKONCE)
+- sprintf (name, "__sparc_get_pc_thunk.%s",
+- reg_names[REGNO (got_register_rtx)] + 1);
+- else
+- ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC",
+- REGNO (got_register_rtx));
+-
++ get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
+ got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
+ }
+
+- insn
+- = gen_load_pcrel_sym (got_register_rtx, sparc_got (), got_helper_rtx);
++ emit_insn (gen_load_pcrel_sym (got_register_rtx, sparc_got (),
++ got_helper_rtx));
+ }
+-
+- emit_insn (insn);
+ }
+
+ /* Ensure that we are not using patterns that are not OK with PIC. */
+@@ -5512,7 +5490,7 @@ save_local_or_in_reg_p (unsigned int regno, int leaf_function)
+ return true;
+
+ /* GOT register (%l7) if needed. */
+- if (got_register_rtx && regno == REGNO (got_register_rtx))
++ if (regno == GLOBAL_OFFSET_TABLE_REGNUM && got_register_rtx)
+ return true;
+
+ /* If the function accesses prior frames, the frame pointer and the return
+@@ -12555,9 +12533,10 @@ static void
+ sparc_file_end (void)
+ {
+ /* If we need to emit the special GOT helper function, do so now. */
+- if (got_helper_needed)
++ if (got_helper_rtx)
+ {
+ const char *name = XSTR (got_helper_rtx, 0);
++ const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
+ #ifdef DWARF2_UNWIND_INFO
+ bool do_cfi;
+ #endif
+@@ -12594,22 +12573,17 @@ sparc_file_end (void)
+ #ifdef DWARF2_UNWIND_INFO
+ do_cfi = dwarf2out_do_cfi_asm ();
+ if (do_cfi)
+- output_asm_insn (".cfi_startproc", NULL);
++ fprintf (asm_out_file, "\t.cfi_startproc\n");
+ #endif
+ if (flag_delayed_branch)
+- {
+- output_asm_insn ("jmp\t%%o7+8", NULL);
+- output_asm_insn (" add\t%%o7, %0, %0", &got_register_rtx);
+- }
++ fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
++ reg_name, reg_name);
+ else
+- {
+- output_asm_insn ("add\t%%o7, %0, %0", &got_register_rtx);
+- output_asm_insn ("jmp\t%%o7+8", NULL);
+- output_asm_insn (" nop", NULL);
+- }
++ fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
++ reg_name, reg_name);
+ #ifdef DWARF2_UNWIND_INFO
+ if (do_cfi)
+- output_asm_insn (".cfi_endproc", NULL);
++ fprintf (asm_out_file, "\t.cfi_endproc\n");
+ #endif
+ }
+
+@@ -13115,10 +13089,7 @@ sparc_init_pic_reg (void)
+ edge entry_edge;
+ rtx_insn *seq;
+
+- /* In PIC mode, we need to always initialize the PIC register if optimization
+- is enabled, because we are called from IRA and LRA may later force things
+- to the constant pool for optimization purposes. */
+- if (!flag_pic || (!crtl->uses_pic_offset_table && !optimize))
++ if (!crtl->uses_pic_offset_table)
+ return;
+
+ start_sequence ();
+diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
+index 0a6e27ffa83..7af62d599b9 100644
+--- a/gcc/config/sparc/sparc.md
++++ b/gcc/config/sparc/sparc.md
+@@ -1604,7 +1604,10 @@
+ (clobber (reg:P O7_REG))]
+ "REGNO (operands[0]) == INTVAL (operands[3])"
+ {
+- return output_load_pcrel_sym (operands);
++ if (flag_delayed_branch)
++ return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0";
++ else
++ return "sethi\t%%hi(%a1-8), %0\n\tadd\t%0, %%lo(%a1-4), %0\n\tcall\t%a2\n\t nop";
+ }
+ [(set (attr "type") (const_string "multi"))
+ (set (attr "length")
+diff --git a/gcc/testsuite/gcc.c-torture/compile/20191108-1.c b/gcc/testsuite/gcc.c-torture/compile/20191108-1.c
+deleted file mode 100644
+index 7929751bb06..00000000000
+--- a/gcc/testsuite/gcc.c-torture/compile/20191108-1.c
++++ /dev/null
+@@ -1,14 +0,0 @@
+-/* PR target/92095 */
+-/* Testcase by Sergei Trofimovich <slyfox@inbox.ru> */
+-
+-typedef union {
+- double a;
+- int b[2];
+-} c;
+-
+-double d(int e)
+-{
+- c f;
+- (&f)->b[0] = 15728640;
+- return e ? -(&f)->a : (&f)->a;
+-}
+diff --git a/gcc/testsuite/gcc.target/sparc/overflow-3.c b/gcc/testsuite/gcc.target/sparc/overflow-3.c
+index 52d6ab2b688..86dddfb09e6 100644
+--- a/gcc/testsuite/gcc.target/sparc/overflow-3.c
++++ b/gcc/testsuite/gcc.target/sparc/overflow-3.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+-/* { dg-options "-O -fno-pie" } */
++/* { dg-options "-O" } */
+
+ #include <stdbool.h>
+ #include <stdint.h>
+diff --git a/gcc/testsuite/gcc.target/sparc/overflow-4.c b/gcc/testsuite/gcc.target/sparc/overflow-4.c
+index c6121b958c3..019feee335c 100644
+--- a/gcc/testsuite/gcc.target/sparc/overflow-4.c
++++ b/gcc/testsuite/gcc.target/sparc/overflow-4.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+-/* { dg-options "-O -fno-pie -mno-vis3 -mno-vis4" } */
++/* { dg-options "-O -mno-vis3 -mno-vis4" } */
+
+ #include <stdbool.h>
+ #include <stdint.h>
+diff --git a/gcc/testsuite/gcc.target/sparc/overflow-5.c b/gcc/testsuite/gcc.target/sparc/overflow-5.c
+index f00283f6e7b..67d4ac38095 100644
+--- a/gcc/testsuite/gcc.target/sparc/overflow-5.c
++++ b/gcc/testsuite/gcc.target/sparc/overflow-5.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+-/* { dg-options "-O -fno-pie -mvis3" } */
++/* { dg-options "-O -mvis3" } */
+
+ #include <stdbool.h>
+ #include <stdint.h>
+--
+2.25.4
+
diff --git a/package/gcc/Config.in.host b/package/gcc/Config.in.host
index dffd052665..2ed159314c 100644
--- a/package/gcc/Config.in.host
+++ b/package/gcc/Config.in.host
@@ -9,7 +9,7 @@ choice
Select the version of gcc you wish to use.
config BR2_GCC_VERSION_ARC
- bool "gcc arc (9.x)"
+ bool "gcc arc (10.x)"
# Only supported architecture
depends on BR2_arc
select BR2_TOOLCHAIN_GCC_AT_LEAST_9
@@ -20,21 +20,11 @@ config BR2_GCC_VERSION_CSKY
depends on BR2_csky
select BR2_TOOLCHAIN_GCC_AT_LEAST_6
-config BR2_GCC_VERSION_7_X
- bool "gcc 7.x"
- depends on !BR2_ARCH_NEEDS_GCC_AT_LEAST_8
- # Broken or unsupported architectures
- depends on !BR2_or1k
- select BR2_TOOLCHAIN_GCC_AT_LEAST_7
-
config BR2_GCC_VERSION_8_X
bool "gcc 8.x"
depends on !BR2_ARCH_NEEDS_GCC_AT_LEAST_9
# Broken or unsupported architectures
depends on !BR2_or1k
- # powerpc spe support has been deprecated since gcc 8.x.
- # https://gcc.gnu.org/ml/gcc/2018-04/msg00102.html
- depends on !BR2_powerpc_SPE
select BR2_TOOLCHAIN_GCC_AT_LEAST_8
config BR2_GCC_VERSION_9_X
@@ -82,11 +72,10 @@ config BR2_GCC_SUPPORTS_DLANG
config BR2_GCC_VERSION
string
- default "7.5.0" if BR2_GCC_VERSION_7_X
default "8.4.0" if BR2_GCC_VERSION_8_X
default "9.3.0" if BR2_GCC_VERSION_9_X
default "10.2.0" if BR2_GCC_VERSION_10_X
- default "arc-2020.03-release" if BR2_GCC_VERSION_ARC
+ default "arc-2020.09-release" if BR2_GCC_VERSION_ARC
default "48152afb96c59733d5bc79e3399bb7b3d4b44266" if BR2_GCC_VERSION_CSKY
config BR2_EXTRA_GCC_CONFIG_OPTIONS
diff --git a/package/gcc/arc-2020.09-release/0001-arc-Refurbish-adc-sbc-patterns.patch b/package/gcc/arc-2020.09-release/0001-arc-Refurbish-adc-sbc-patterns.patch
new file mode 100644
index 0000000000..3292b26a4e
--- /dev/null
+++ b/package/gcc/arc-2020.09-release/0001-arc-Refurbish-adc-sbc-patterns.patch
@@ -0,0 +1,243 @@
+From b92c22b144d063c4436a6693045ceb57d344c495 Mon Sep 17 00:00:00 2001
+From: Claudiu Zissulescu <claziss@synopsys.com>
+Date: Wed, 11 Nov 2020 12:31:10 +0200
+Subject: [PATCH] arc: Refurbish adc/sbc patterns
+
+The adc/sbc patterns were unecessary spliting, remove that and
+associated functions.
+
+gcc/ChangeLog:
+
+2020-10-11 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc-protos.h (arc_scheduling_not_expected): Remove
+ it.
+ (arc_sets_cc_p): Likewise.
+ (arc_need_delay): Likewise.
+ * config/arc/arc.c (arc_sets_cc_p): Likewise.
+ (arc_need_delay): Likewise.
+ (arc_scheduling_not_expected): Likewise.
+ * config/arc/arc.md: Convert adc/sbc patterns to simple
+ instruction definitions.
+
+Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
+
+Downloaded from upstream commit
+https://github.com/foss-for-synopsys-dwc-arc-processors/gcc/commit/b92c22b144d063c4436a6693045ceb57d344c495
+
+Signed-off-by: Bernd Kuhls <bernd.kuhls@t-online.de>
+---
+ gcc/config/arc/arc-protos.h | 3 --
+ gcc/config/arc/arc.c | 53 ---------------------
+ gcc/config/arc/arc.md | 95 +++++++++++--------------------------
+ 3 files changed, 29 insertions(+), 122 deletions(-)
+
+diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
+index c72d78e3b9e..de4cf47c818 100644
+--- a/gcc/config/arc/arc-protos.h
++++ b/gcc/config/arc/arc-protos.h
+@@ -90,10 +90,7 @@ extern void split_subsi (rtx *);
+ extern void arc_split_move (rtx *);
+ extern const char *arc_short_long (rtx_insn *insn, const char *, const char *);
+ extern rtx arc_regno_use_in (unsigned int, rtx);
+-extern bool arc_scheduling_not_expected (void);
+-extern bool arc_sets_cc_p (rtx_insn *insn);
+ extern int arc_label_align (rtx_insn *label);
+-extern bool arc_need_delay (rtx_insn *insn);
+ extern bool arc_text_label (rtx_insn *insn);
+
+ extern bool arc_short_comparison_p (rtx, int);
+diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
+index 5a7b0cb6696..c3ee9181f93 100644
+--- a/gcc/config/arc/arc.c
++++ b/gcc/config/arc/arc.c
+@@ -10341,59 +10341,6 @@ arc_attr_type (rtx_insn *insn)
+ return get_attr_type (insn);
+ }
+
+-/* Return true if insn sets the condition codes. */
+-
+-bool
+-arc_sets_cc_p (rtx_insn *insn)
+-{
+- if (NONJUMP_INSN_P (insn))
+- if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))
+- insn = seq->insn (seq->len () - 1);
+- return arc_attr_type (insn) == TYPE_COMPARE;
+-}
+-
+-/* Return true if INSN is an instruction with a delay slot we may want
+- to fill. */
+-
+-bool
+-arc_need_delay (rtx_insn *insn)
+-{
+- rtx_insn *next;
+-
+- if (!flag_delayed_branch)
+- return false;
+- /* The return at the end of a function needs a delay slot. */
+- if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
+- && (!(next = next_active_insn (insn))
+- || ((!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) != SEQUENCE)
+- && arc_attr_type (next) == TYPE_RETURN))
+- && (!TARGET_PAD_RETURN
+- || (prev_active_insn (insn)
+- && prev_active_insn (prev_active_insn (insn))
+- && prev_active_insn (prev_active_insn (prev_active_insn (insn))))))
+- return true;
+- if (NONJUMP_INSN_P (insn)
+- ? (GET_CODE (PATTERN (insn)) == USE
+- || GET_CODE (PATTERN (insn)) == CLOBBER
+- || GET_CODE (PATTERN (insn)) == SEQUENCE)
+- : JUMP_P (insn)
+- ? (GET_CODE (PATTERN (insn)) == ADDR_VEC
+- || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
+- : !CALL_P (insn))
+- return false;
+- return num_delay_slots (insn) != 0;
+-}
+-
+-/* Return true if the scheduling pass(es) has/have already run,
+- i.e. where possible, we should try to mitigate high latencies
+- by different instruction selection. */
+-
+-bool
+-arc_scheduling_not_expected (void)
+-{
+- return cfun->machine->arc_reorg_started;
+-}
+-
+ /* Code has a minimum p2 alignment of 1, which we must restore after
+ an ADDR_DIFF_VEC. */
+
+diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
+index f91adbc0d94..c635b69ddd5 100644
+--- a/gcc/config/arc/arc.md
++++ b/gcc/config/arc/arc.md
+@@ -2847,43 +2847,25 @@ archs4x, archs4xd"
+ (set_attr "type" "compare")
+ (set_attr "length" "4,4,8")])
+
+-; w/c/c comes first (rather than w/0/C_0) to prevent the middle-end
+-; needlessly prioritizing the matching constraint.
+-; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional
+-; execution is used where possible.
+-(define_insn_and_split "adc"
+- [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w")
+- (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0))
+- (match_operand:SI 1 "nonmemory_operand"
+- "%c,0,c,0,cCal"))
+- (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))]
++(define_insn "adc"
++ [(set (match_operand:SI 0 "register_operand" "=r, r,r,r, r,r")
++ (plus:SI
++ (plus:SI
++ (ltu:SI (reg:CC_C CC_REG) (const_int 0))
++ (match_operand:SI 1 "nonmemory_operand" "%r, 0,r,0,Cal,r"))
++ (match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I, r,Cal")))]
+ "register_operand (operands[1], SImode)
+ || register_operand (operands[2], SImode)"
+ "@
+- adc %0,%1,%2
+- add.cs %0,%1,1
+- adc %0,%1,%2
+- adc %0,%1,%2
+- adc %0,%1,%2"
+- ; if we have a bad schedule after sched2, split.
+- "reload_completed
+- && !optimize_size && (!TARGET_ARC600_FAMILY)
+- && arc_scheduling_not_expected ()
+- && arc_sets_cc_p (prev_nonnote_insn (insn))
+- /* If next comes a return or other insn that needs a delay slot,
+- expect the adc to get into the delay slot. */
+- && next_nonnote_insn (insn)
+- && !arc_need_delay (next_nonnote_insn (insn))
+- /* Restore operands before emitting. */
+- && (extract_insn_cached (insn), 1)"
+- [(set (match_dup 0) (match_dup 3))
+- (cond_exec
+- (ltu (reg:CC_C CC_REG) (const_int 0))
+- (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))))]
+- "operands[3] = simplify_gen_binary (PLUS, SImode, operands[1], operands[2]);"
++ adc\\t%0,%1,%2
++ add.cs\\t%0,%1,1
++ adc\\t%0,%1,%2
++ adc\\t%0,%1,%2
++ adc\\t%0,%1,%2
++ adc\\t%0,%1,%2"
+ [(set_attr "cond" "use")
+ (set_attr "type" "cc_arith")
+- (set_attr "length" "4,4,4,4,8")])
++ (set_attr "length" "4,4,4,4,8,8")])
+
+ ; combiner-splitter cmp / scc -> cmp / adc
+ (define_split
+@@ -3015,7 +2997,7 @@ archs4x, archs4xd"
+ DONE;
+ }
+ emit_insn (gen_sub_f (l0, l1, l2));
+- emit_insn (gen_sbc (h0, h1, h2, gen_rtx_REG (CCmode, CC_REG)));
++ emit_insn (gen_sbc (h0, h1, h2));
+ DONE;
+ ")
+
+@@ -3030,44 +3012,25 @@ archs4x, archs4xd"
+ (set_attr "type" "cc_arith")
+ (set_attr "length" "4")])
+
+-; w/c/c comes first (rather than Rcw/0/C_0) to prevent the middle-end
+-; needlessly prioritizing the matching constraint.
+-; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional execution
+-; is used where possible.
+-(define_insn_and_split "sbc"
+- [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w")
+- (minus:SI (minus:SI (match_operand:SI 1 "nonmemory_operand"
+- "c,0,c,0,cCal")
+- (ltu:SI (match_operand:CC_C 3 "cc_use_register")
+- (const_int 0)))
+- (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))]
++(define_insn "sbc"
++ [(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r,r,r,r")
++ (minus:SI
++ (minus:SI
++ (match_operand:SI 1 "nonmemory_operand" "r, 0,r,0, r,Cal")
++ (ltu:SI (reg:CC_C CC_REG) (const_int 0)))
++ (match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I,Cal,r")))]
+ "register_operand (operands[1], SImode)
+ || register_operand (operands[2], SImode)"
+ "@
+- sbc %0,%1,%2
+- sub.cs %0,%1,1
+- sbc %0,%1,%2
+- sbc %0,%1,%2
+- sbc %0,%1,%2"
+- ; if we have a bad schedule after sched2, split.
+- "reload_completed
+- && !optimize_size && (!TARGET_ARC600_FAMILY)
+- && arc_scheduling_not_expected ()
+- && arc_sets_cc_p (prev_nonnote_insn (insn))
+- /* If next comes a return or other insn that needs a delay slot,
+- expect the adc to get into the delay slot. */
+- && next_nonnote_insn (insn)
+- && !arc_need_delay (next_nonnote_insn (insn))
+- /* Restore operands before emitting. */
+- && (extract_insn_cached (insn), 1)"
+- [(set (match_dup 0) (match_dup 4))
+- (cond_exec
+- (ltu (reg:CC_C CC_REG) (const_int 0))
+- (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1))))]
+- "operands[4] = simplify_gen_binary (MINUS, SImode, operands[1], operands[2]);"
++ sbc\\t%0,%1,%2
++ sub.cs\\t%0,%1,1
++ sbc\\t%0,%1,%2
++ sbc\\t%0,%1,%2
++ sbc\\t%0,%1,%2
++ sbc\\t%0,%1,%2"
+ [(set_attr "cond" "use")
+ (set_attr "type" "cc_arith")
+- (set_attr "length" "4,4,4,4,8")])
++ (set_attr "length" "4,4,4,4,8,8")])
+
+ (define_insn "sub_f"
+ [(set (reg:CC CC_REG)
diff --git a/package/gcc/arc-2020.03-release/0100-uclibc-conf.patch b/package/gcc/arc-2020.09-release/0100-uclibc-conf.patch
index d354baf81f..d354baf81f 100644
--- a/package/gcc/arc-2020.03-release/0100-uclibc-conf.patch
+++ b/package/gcc/arc-2020.09-release/0100-uclibc-conf.patch
diff --git a/package/gcc/gcc.hash b/package/gcc/gcc.hash
index 5f38572beb..2208095a29 100644
--- a/package/gcc/gcc.hash
+++ b/package/gcc/gcc.hash
@@ -1,5 +1,3 @@
-# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-7.5.0/sha512.sum
-sha512 fe716cc19f2e3255d3a8b1b8290777bf769c6d98e6e0b07b81a3d6ad43f8af74cb170dfa18b1555dbfcd3f55ae582b91a286ccef496b9b65c1579902f96a1f60 gcc-7.5.0.tar.xz
# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-8.4.0/sha512.sum
sha512 6de904f552a02de33b11ef52312bb664396efd7e1ce3bbe37bfad5ef617f133095b3767b4804bc7fe78df335cb53bc83f1ac055baed40979ce4c2c3e46b70280 gcc-8.4.0.tar.xz
# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-9.3.0/sha512.sum
@@ -8,7 +6,7 @@ sha512 4b9e3639eef6e623747a22c37a904b4750c93b6da77cf3958d5047e9b5ebddb7eebe091c
sha512 42ae38928bd2e8183af445da34220964eb690b675b1892bbeb7cd5bb62be499011ec9a93397dba5e2fb681afadfc6f2767d03b9035b44ba9be807187ae6dc65e gcc-10.2.0.tar.xz
# Locally calculated (fetched from Github)
-sha512 09ad77fce757d77f2db49cd049b78861abfa5c1c6c3be76228815ec2b15810c1985525c48b0300e83e88f3fa33dee0062f34790cc8b6bc2fa6b0301595acf42b gcc-arc-2020.03-release.tar.gz
+sha512 b0853e2b1c5998044392023fa653e399e74118c46e616504ac59e1a2cf27620f94434767ce06b6cf4ca3dfb57f81d6eda92752befaf095ea5e564a9181b4659c gcc-arc-2020.09-release.tar.gz
# Locally calculated (fetched from Github)
sha512 2de7cf47333a4092b02d3bb98f4206f14966f1d139a724d09cf3b22f8a43ae0c704f33e6477d6367a03c29b265480dc900169e9d417006c5d46f0ae446b8c6f1 gcc-or1k-musl-5.4.0-20170218.tar.gz
# Locally calculated (fetched from https://github.com/c-sky/gcc)
diff --git a/package/gcc/gcc.mk b/package/gcc/gcc.mk
index b834269adc..5e419f7ede 100644
--- a/package/gcc/gcc.mk
+++ b/package/gcc/gcc.mk
@@ -98,6 +98,12 @@ ifeq ($(BR2_ENABLE_DEBUG),y)
GCC_COMMON_TARGET_CFLAGS += -Wno-error
endif
+# Make sure libgcc & libstdc++ always get built with -matomic on ARC700
+ifeq ($(GCC_TARGET_CPU):$(BR2_ARC_ATOMIC_EXT),arc700:y)
+GCC_COMMON_TARGET_CFLAGS += -matomic
+GCC_COMMON_TARGET_CXXFLAGS += -matomic
+endif
+
# Propagate options used for target software building to GCC target libs
HOST_GCC_COMMON_CONF_ENV += CFLAGS_FOR_TARGET="$(GCC_COMMON_TARGET_CFLAGS)"
HOST_GCC_COMMON_CONF_ENV += CXXFLAGS_FOR_TARGET="$(GCC_COMMON_TARGET_CXXFLAGS)"
@@ -116,17 +122,7 @@ endif
ifeq ($(BR2_USE_WCHAR)$(BR2_TOOLCHAIN_HAS_LIBQUADMATH),yy)
HOST_GCC_COMMON_CONF_OPTS += --enable-libquadmath
else
-HOST_GCC_COMMON_CONF_OPTS += --disable-libquadmath
-endif
-
-# Disable libsanitizer due to a build issue with gcc 7.5 and glibc 2.31.
-# It would require to backport the following upstream commit
-# https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=4abc46b51af5751d657764d0c44b8a4aeed06302
-# but it conflict with gcc 7.5 libsanitizer code.
-# Disable libsanitizer since the gcc 7.5 branch is now closed
-# (unmaintained) and it's not a trivial merge.
-ifeq ($(BR2_TOOLCHAIN_BUILDROOT_GLIBC)$(BR2_GCC_VERSION_7_X),yy)
-HOST_GCC_COMMON_CONF_OPTS += --disable-libsanitizer
+HOST_GCC_COMMON_CONF_OPTS += --disable-libquadmath --disable-libquadmath-support
endif
# libsanitizer requires wordexp, not in default uClibc config. Also
@@ -141,6 +137,14 @@ ifeq ($(BR2_sparc)$(BR2_sparc64),y)
HOST_GCC_COMMON_CONF_OPTS += --disable-libsanitizer
endif
+# The logic in libbacktrace/configure.ac to detect if __sync builtins
+# are available assumes they are as soon as target_subdir is not
+# empty, i.e when cross-compiling. However, some platforms do not have
+# __sync builtins, so help the configure script a bit.
+ifeq ($(BR2_TOOLCHAIN_HAS_SYNC_4),)
+HOST_GCC_COMMON_CONF_ENV += target_configargs="libbacktrace_cv_sys_sync=no"
+endif
+
# TLS support is not needed on uClibc/no-thread and
# uClibc/linux-threads, otherwise, for all other situations (glibc,
# musl and uClibc/NPTL), we need it.
@@ -219,10 +223,18 @@ endif
# Enable proper double/long double for SPE ABI
ifeq ($(BR2_powerpc_SPE),y)
HOST_GCC_COMMON_CONF_OPTS += \
+ --enable-obsolete \
--enable-e500_double \
--with-long-double-128
endif
+# Set default to Secure-PLT to prevent run-time
+# generation of PLT stubs (supports RELRO and
+# SELinux non-exemem capabilities)
+ifeq ($(BR2_powerpc),y)
+HOST_GCC_COMMON_CONF_OPTS += --enable-secureplt
+endif
+
# PowerPC64 big endian by default uses the elfv1 ABI, and PowerPC 64
# little endian by default uses the elfv2 ABI. However, musl has
# decided to use the elfv2 ABI for both, so we force the elfv2 ABI for
@@ -241,6 +253,11 @@ HOST_GCC_COMMON_CONF_OPTS += \
--with-long-double-128
endif
+ifeq ($(BR2_s390x),y)
+HOST_GCC_COMMON_CONF_OPTS += \
+ --with-long-double-128
+endif
+
HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_CROSS_PATH_SUFFIX='".br_real"'
# For gcc-initial, we need to tell gcc that the C library will be
@@ -271,11 +288,6 @@ HOST_GCC_COMMON_CCACHE_HASH_FILES += \
ifeq ($(BR2_xtensa),y)
HOST_GCC_COMMON_CCACHE_HASH_FILES += $(ARCH_XTENSA_OVERLAY_TAR)
endif
-ifeq ($(ARCH),powerpc)
-ifneq ($(BR2_SOFT_FLOAT),)
-HOST_GCC_COMMON_CCACHE_HASH_FILES += package/gcc/$(GCC_VERSION)/1000-powerpc-link-with-math-lib.patch.conditional
-endif
-endif
# _CONF_OPTS contains some references to the absolute path of $(HOST_DIR)
# and a reference to the Buildroot git revision (BR2_VERSION_FULL),